Uniform dielectric layer and method to form same

ABSTRACT

An exemplary embodiment of the present invention discloses a method for forming a forming a storage capacitor having a uniform dielectric film, by a the steps of: forming a bottom electrode of the storage capacitor and an insulation material about the bottom electrode, the bottom electrode comprises a nitridation receptive material and the insulation material comprises a nitridation resistive material; depositing a layer of non-doped silicon to a thickness of 20 Å or less over the bottom electrode and the insulation material; converting the silicon layer to a silicon nitride compound; depositing a silicon nitride of uniform thickness directly on the silicon nitride compound while using the silicon nitride compound as a nitride-nucleation enhancing surface; exposing the silicon nitride compound and the silicon nitride layer to an oxidation ambient to form a storage capacitor dielectric film; and then forming a top electrode of the storage capacitor over the storage capacitor dielectric film.

FIELD OF THE INVENTION

[0001] This invention relates to semiconductor fabrication processingand more particularly to a method for forming uniform dielectric filmsused in semiconductor devices, such as dynamic random access memories(DRAMs).

BACKGROUND OF THE INVENTION

[0002] In the manufacturing of dynamic random access memories (DRAMs)the size of the memory cell is the main contributing factor to thedensity and overall size of the device. A manufacturer of DRAMs hasmotivation to increase the storage capability, while maintaining thesmallest die size possible, as the smaller die size results in a lowercost per device. As mentioned, the main contributor to the size of amemory device is the amount of space required for each storage cell thatmakes up the storage array. In that regard, DRAM fabrication engineershave focused on structures, on materials to make the structures and onmethods to fabricate the structures necessary to make a storage cell.

[0003] To save space, the capacitor of the storage cell must reduce insize and yet maintain adequate capacitance to retain a sufficient chargeduring DRAM operation. There are several approaches to the capacitordesign, for example trench capacitors formed in the substrate of a waferor a stacked capacitor formed above the wafer substrate, to name two.Regardless of the design chosen, the size of the capacitor must bereduced and yet maintain sufficient capacitance as mentioned previously.Two of the main contributors to capacitance are the surface area of thecapacitor plates and the dielectric quality of the insulator separatingthe capacitor plates. Major engineering efforts have gone into bothareas.

[0004] In regards to dielectric quality, thin film dielectrics havinghigh dielectric constant characteristics have emerged as the dielectricof choice, as the thinnest film that can be placed between the capacitorplates to prevent dielectric breakdown when a charge is present on thecapacitor plates, drastically increases capacitance. With increasedcapacitance, the overall size of the capacitor can be reduced. However,thin film dielectrics present some challenges in fabricating thecomplete storage cell structure, which includes a storage cell accesstransistor and a storage capacitor.

[0005] One main challenge and a critical area of concern is oxidationpunch through, which is important to avoid when forming thin filmdielectrics. Oxidation punch through refers to the mechanism of atomicoxygen diffusing completely through a dielectric film. In the case of acapacitor cell dielectric, if oxidation punch through was allowed tooccur a portion of an underlying diffusion region of an accesstransistor would become oxidized and thus diminish the transistor'soperating characteristics. It is critical that oxidation punch throughbe at least reduced or ideally avoided altogether. When dealing withthin film dielectrics the dielectric film needs to be thick enough tosufficiently to reduce oxidation punch through. The minimum thickness ofthe dielectric film is dependent on the required oxidation time andtemperature used and is particularly critical to maintain when using thedielectric film as a capacitor cell dielectric. It is also importantthat the dielectric film be a uniform film in order to minimize theoverall thickness of the film.

[0006] One of the thin dielectric films of choice is nitride (i.e.,silicon nitride) as nitride possesses sufficient dielectric constantcharacteristics and can be deposited as a very thin layer (less than 100Å). However, a nitride film of this thickness is difficult to deposituniformly on a surface that is made up of different types of material,especially materials that are not receptive to nitride deposition. Whentrying to deposit thin nitride films on different types of materials,the surface free energy involved in the deposition reaction is differentfor each of the different types of materials. Thus the different typesof materials do not allow the formation of a uniform dielectric film,particularly layers less than 100 Å.

[0007] The present invention teaches a method to successfully formuniform dielectric films as will become apparent to those skilled in theart from the following disclosure.

SUMMARY OF THE INVENTION

[0008] The present invention teaches a method for forming a uniformdielectric film in a semiconductor assembly. First, a nonconductivenitride-nucleation enhancing layer is formed over a semiconductorassembly that comprises a nitridation receptive material and anitridation resistive material. For purposes of the present invention, anitride-nucleation enhancing layer is a material that will readilyaccept the bonding of nitrogen atoms to the material itself. Next, asilicon nitride layer is formed over the nonconductivenitride-nucleation enhancing layer. The nonconductive nitride-nucleationenhancing layer provides for the silicon nitride layer to have a uniformthickness over both the nitridation receptive material and thenitridation resistive material.

[0009] The above method can be applied to devices that would benefitfrom the use of a thin dielectric film, such as a memory device (i.e.,DRAM, floating gate device, etc.) that operates by storing a charge. Forexample, one implementation of the present invention is to form anitride dielectric layer that is less than 100 Å in thickness for theintended use as a storage capacitor dielectric.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a cross-sectional view depicting a semiconductorsubstrate comprising portions of a memory storage cell having a storagecell access transistor and a bottom electrode for a storage capacitorand a conformal layer of polysilicon formed thereover.

[0011]FIG. 2 is a subsequent cross-sectional view taken from FIG. 1after converting the polysilicon layer to silicon nitride using athermal nitridation step.

[0012]FIG. 3 is a subsequent cross-sectional view taken from FIG. 2following the formation of a thin dielectric material to a desiredthickness, over the silicon nitride layer.

[0013]FIG. 4 is a subsequent cross-sectional view taken from FIG. 3following the formation of a top electrode for the storage capacitor.

DETAILED DESCRIPTION OF THE INVENTION

[0014] An exemplary implementation of the present invention is directedto a process for forming a uniform dielectric layer used in asemiconductor device as depicted in FIGS. 1-4.

[0015] The following exemplary implementation is in reference to thefabrication of dynamic random access memory (DRAM) device. While theconcepts of the present invention are conducive to the fabrication ofDRAMs, the concepts taught herein may be applied to other semiconductordevices that would likewise benefit from the use of a thin dielectricfilm that will substantially reduce oxidation punch through. Therefore,the depiction of the present invention in reference to the manufactureof a DRAM (the preferred embodiment), is not meant to limit the extentto which one skilled in the art might apply the concepts taughthereinafter.

[0016] Referring to FIG. 1, a semiconductive substrate 10, such as asilicon wafer, is prepared for the processing steps of the presentinvention. Transistor gate conductors (word lines) 13 and the transistordiffusion regions 11, separated by field oxide region 12, are formed byconventional DRAM fabrication methods. A layer of planarized insulationmaterial 14 is formed over diffusion regions 11 and word lines 12. Inone exemplary implementation, material 13 is a reflowable glass, such asBoroPhosphoSilicate Glass (BPSG). A cavity is patterned and etched intomaterial 14 to receive a conductive material, such as polysilicon orhemispherical-grained (HSG) silicon, that is formed and patterned toproduce a bottom plate 15 of a storage capacitor.

[0017] Generally, insulating materials such as BPSG, oxides and thelike, do not provide atomic bonding surfaces that are receptive tonitridation (the bonding of nitrogen atoms to a given material). Forpurposes of the present invention these materials are labeled as“nitridation resistive materials.” Generally, conductive materials andsemiconductive materials, such as metals and silicon, respectively, doprovide atomic bonding surfaces that are receptive to nitridation. Forpurposes of the present invention these materials are labeled as“nitridation receptive materials.”

[0018] It is at this point that an implementation of an embodiment ofthe present invention is employed to fabricate a storage celldielectric. A conformal nonconductive nitride-nucleation enhancinglayer, such as non-conductive silicon layer 16 is formed directly oninsulation material 14 and conductive bottom plate 15. The presence oflayer 16 is critical for the formation of the cell dielectric. Thepurpose of layer 16 is to provide a uniform nucleation surface for asubsequent deposition of a cell dielectric material as layer 16 willpossess a consistent surface free energy for the subsequent deposition.The ideal nitride-nucleation enhancing layer will allow almost immediateformation of a nitride film during the film deposition step, meaning thetime required for nucleation, before the actual film deposition occurs,will be nearly zero. An enhancing layer that allows actual filmdeposition to occur less than 10 seconds from initial deposition startup time is desired. In that light, it is preferred that layer 16 benon-doped polysilicon deposited to a thickness of approximately 5-20 Å,or less, is possible in the particular process employed. Ideally, acontinuous monolayer would be formed; although even a discontinuouslayer (including a monolayer) is useful in accordance with the presentinvention. Non-doped polysilicon cannot be used as a cell dielectric byitself as polysilicon material is much too leaky. Non-doped polysiliconis a polysilicon layer that contains too small of a concentration ofconductive impurities for the material to be considered to beconductive. However the conduction of polysilicon can be secured ifconductive impurities are diffused into it. Therefore, it is preferredto minimize the thickness of the non-doped polysilicon used for layer16. Conductively doped polysilicon can be used, however, an extrameasure must be taken as discussed below.

[0019] Referring now to FIG. 2, if desired, layer 16 of FIG. 1 issubjected to a thermal nitridation step in order to convert at least aportion of the silicon layer to silicon nitride layer 17. A typicalthermal nitridation step can be used, such as releasing a nitrogencontaining gas (NH₃) into a fabrication chamber that maintains atemperature of greater than 400° C. If it is desired to use a conductivematerial for layer 16, such as conductively doped polysilicon, theentire conductive material (i.e., a silicon film) must be converted tosilicon nitride in order to avoid creating a conductive path betweenseparate bottom electrodes 15. However, if so desired, this thermalnitridation step may be skipped if layer 16 is a non-conductive layer,such as non-doped polysilicon 16.

[0020] Referring now to FIG. 3, a nitride layer 18 is deposited to athickness such that when combined with nucleation layer 16 the totalthickness is approximately less than 100 Å (50 Å or less is preferred).The nucleation layer 16 or converted nitride layer 17 (if converted tonitride) provides a consistent nucleation surface for the deposition ofnitride layer 18, thus resulting in a nitride film of uniform thicknessoverlying material 13 (a nitridation resistive material) and bottomelectrode 15 (a nitridation receptive material). Nitride layer 18 can beformed insitu after the formation of the silicon layer by simplypresenting a silicon source gas (such as SiH₄, diclorosilane andSiH₂Cl₂) and a nitrogen source gas (such as NH₃) to the depositionchamber using deposition conditions suitable for both polysilicon andnitride deposition.

[0021] Referring now to FIG. 4, nucleation layer 16 (FIG. 1), whethersilicon or a converted silicon nitride layer (as shown at 17 in FIG. 2)combined with deposited silicon nitride layer 18 (FIG. 3) are nowrepresented as cell nitride dielectric layer 19. With a consistent,uniform thickness less than 100 Å (50 Å or less is preferred), cellnitride dielectric layer 19 now possesses a thickness that is sufficientto prevent oxidation punch through from a subsequent wet oxidation stepneeded to fill any pinholes in layer 19. Oxidation punch through refersto the mechanism of atomic oxygen diffusing completely through adielectric film and diffusing all the way to an implanted region. Inthis example, if punch through were allowed, oxygen atoms would possiblyreach implanted regions 11, which would result in oxidation of theimplanted source/drain regions 11. Typically, a nitride film used as acell dielectric is subjected to an oxidation ambient, at a moderatetemperature (750-850° C.) and for a prolonged period of time. If oxygenatoms reach an implanted diffusion region, the region will oxidize whichmeans the oxidation process will consume some of the silicon in theimplanted diffusion region and thus adversely affect transistoroperation. Using the methods of the present invention the oxidation ofcell dielectric layer 19 would limit punch through and thus greatlylimit the oxidation of the implanted diffusion regions 11.

[0022] Continuing with FIG. 4, a top storage capacitor electrode isfabricated by the formation of a conductive layer 18 to complete storagecapacitor formation. From this point on the device is completed asdictated by the fabrication process used by those skilled in the art.

[0023] Though an exemplary implementation of the present inventiondescribed above teaches the use of silicon nitride in a storagecapacitor, the method would also apply to other dielectric films, suchas TaO₅, and other devices, such as a floating gate device. Using TaO₅for example would require forming a layer of tantalum for layer 16,converting it to TaO₅ (layer 17) and depositing a layer of TaO₅ (layer18) to a desired thickness.

[0024] It is to be understood that although the present invention hasbeen described with reference to a preferred embodiment, variousmodifications, known to those skilled in the art, may be made to theprocess steps presented herein without departing from the invention asrecited in the several claims appended hereto.

What is claimed is:
 1. A method for forming a uniform dielectric film in a semiconductor assembly, said method comprising the steps of: forming a nonconductive nitride-nucleation enhancing layer over said semiconductor assembly, said semiconductor assembly comprising a nitridation receptive material and a nitridation resistive material; forming a silicon nitride layer directly on said nonconductive nitride-nucleation enhancing layer, whereby said nonconductive nitride-nucleation enhancing layer provides for said silicon nitride layer to have a uniform thickness over said nitridation receptive material and said nitridation resistive material.
 2. The method as recited in claim 1 , wherein said step of forming a nonconductive nitride-nucleation enhancing layer and step of forming a silicon nitride layer comprise depositing said layers to a combined thickness less than 100 Å.
 3. The method as recited in claim 1 , wherein said steps of forming a nonconductive nitride-nucleation enhancing layer and of forming a silicon nitride layer are performed insitu.
 4. The method as recited in claim 1 , wherein said step of forming a nonconductive nitride-nucleation enhancing layer comprises depositing a silicon layer to a thickness of 20 Å or less.
 5. A method for forming a uniform dielectric film in a semiconductor assembly, said method comprising the steps of: forming a nonconductive silicon layer over said semiconductor assembly, said semiconductor assembly comprising a nitridation receptive material and a nitridation resistive material; converting at least a portion of said nonconductive silicon layer to a silicon nitride compound; forming a silicon nitride layer directly on said nonconductive silicon layer while using the surface of said silicon nitride compound as a nucleation surface; whereby said nonconductive silicon layer provides for said silicon nitride layer to have a uniform thickness over said nitridation receptive material and said nitridation resistive material.
 6. The method as recited in claim 5 , further comprising the step of: exposing said silicon nitride compound and said silicon nitride layer to an oxidation ambient.
 7. The method as recited in claim 5 , wherein said step of forming a nonconductive silicon layer comprises depositing said layer to a thickness of 20 Å or less.
 8. The method as recited in claim 5 , wherein said step of depositing a silicon nitride layer comprises depositing said silicon nitride layer to a thickness such that the combined thickness of said silicon nitride compound and said silicon nitride layer is 50 Å or less.
 9. The method as recited in claim 5 , wherein said steps of forming a nonconductive silicon layer and of forming a silicon nitride layer are performed insitu.
 10. A method for forming a uniform dielectric film for a memory device, said method comprising the steps of: forming a nonconductive silicon layer over a semiconductor assembly comprising a conductive material serving as a capacitor storage electrode isolated by an nitridation resistive material; converting at least a portion of said nonconductive silicon layer to a silicon nitride compound; forming a silicon nitride layer directly on said nonconductive silicon layer while using the surface of said silicon nitride compound as a nucleation surface; whereby, said nonconductive silicon layer provides for said silicon nitride layer to have a uniform thickness over said conductive material and said nitridation resistive material.
 11. A method for forming a storage capacitor having a uniform dielectric film, said method comprising the steps of: forming a bottom electrode of said storage capacitor and an insulation material about said bottom electrode, said bottom electrode comprising a nitridation receptive material and said insulation material comprising a nitridation resistive material; depositing a layer of non-doped silicon to a thickness of 20 Å or less over said bottom electrode and said insulation material; converting said silicon layer to a silicon nitride compound; depositing a silicon nitride of uniform thickness directly on said silicon nitride compound while using said silicon nitride compound as a nitride-nucleation enhancing surface; exposing said silicon nitride compound and said silicon nitride layer to an oxidation ambient to form a storage capacitor dielectric film; and forming a top electrode of said storage capacitor over said storage capacitor dielectric film.
 12. A method for forming a uniform dielectric film in a semiconductor fabrication process, said method comprising the steps of: forming a layer having a consistent surface free energy to a chemical reaction over a semiconductor assembly, said semiconductor assembly comprising a nitridation receptive material and a nitridation resistive material; converting said layer to a dielectric chemical compound; depositing a dielectric layer directly on said dielectric compound while using the surface of said dielectric compound as a nucleation surface, said dielectric compound and said dielectric layer each possessing a chemically similar dielectric material.
 13. The method as recited in claim 12 , wherein said semiconductor fabrication process comprises a floating gate fabrication process used to fabricate the floating gate dielectric.
 14. The method as recited in claim 12 , wherein said step of forming a layer comprises depositing a layer of non-doped silicon.
 15. The method as recited in claim 12 , wherein said step of converting said layer comprises subjecting said layer of non-doped silicon to a thermal nitridation step by releasing nitrogen containing gas into a fabrication chamber that maintains a temperature of around 400° or greater.
 16. The method as recited in claim 12 , wherein said step of converting said layer comprises subjecting said layer of non-doped silicon to a plasma nitridation step by releasing nitrogen containing gas into a fabrication chamber that maintains a temperature of around 400° or greater.
 17. A semiconductor assembly comprising: a nitride resistive material and a nitride receptive material, both said materials covered by a nitride layer with substantially consistent thickness over both said materials, wherein a surface of said nitride resistive material and a surface of said nitride receptive material is less than 100 Å from an outer most surface of said nitride layer.
 18. A memory array in a semiconductor assembly comprising: a capacitor storage electrode isolated by insulation material, said capacitor storage electrode being made of a nitride receptive material and said insulation material being made of a nitride resistive material; a nitride layer with substantially consistent thickness covering said capacitor storage electrode and said insulation material; wherein a surface of said capacitor electrode and a surface of said insulation material is less than 100 Å from an outer most surface of said nitride layer. 